TI Adds Cleveland to MSP430 Seminar Schedule
Saturday, October 27th, 2007
Cleveland is a late addition to the MSP430 Advanced Technology Seminar schedule. TI promises the latest information on new releases and in-depth discussions on low-power applications straight from the experts.
If you are new to the 430 series, its claim to fame is its ultra-low-power 16-bit architecture supporting cost-sensitive, battery operated applications. MSP430s feature a mixed-signal design and a high performance 16-bit RISC CPU. The architecture is designed to minimize power use through a variety of lower power modes (LPM0-LPM4), shorter transition times between modes and faster execution program code. The faster the chip starts up and executes the application the more time it can spend sleeping and saving precious power.
This event focuses on the MSP430F2xx series of devices.
Additional information and a registration links are available here. Look for Microsockets at the Cleveland event on November 29.
