Renesas RX – A New Prescription for CISC
Sunday, November 11th, 2007
On November 8, 2007, Renesas provided an update on the progress of its new 16/32-bit CISC architecture. The new family finally has a name- RX Family – where RX implies ”Renesas eXtreme.”
The new CPU is the long-term replacement or migration path for the collection of products created by the merging of Mitsubishi and Hitachi product portfolios. The RX replaces the H8S, M16C, M32C, R32C and H8SX with a unified, high-performance processor architecture.
- 200 MHz operating frequency
- 1.25 MIPS/MHz performance
- 30% reduction in code size compared to previous CISC architectures
- Low power consumption – 0.03mA/MHz
The boosts in operating frequency and instruction efficiency promise a 12.5 times increase in performance over existing Renesas CISC controllers.
Much of the presentation is a rehash of the May 2007 announcement with some clarifications and specifics that reflect the progress of development. Here are some key differences from previous announcements.
- Silicon availability in Q2 CY2009 – moved up from Q3 CY2009
- 1/3 power consumption measured mA/MHz – down from 1/2 versus M16 and H8
- Processing performance at 1.25 MIPS/MHz up from 1.0 MIPS/MHz
Other than the name, which is better suited for an energy drink or deodorant, there is a lot to like hidden in the details of the presentation.
- 32-bit multiplier, divider and MAC (32 x 32 + 80 bits)
- Variable length instructions optimized for common operations
- 16 32-bit registers to support compiler optimization
- Selectable big-endian (H8S) and little-endian (M16C) data access
- C-friendly addressing modes for improved pointer manipulations
- C-level compatibility with previous devices and common peripherals
- On-chip single-precision FPU that utilizes the general register set
Processor specifications are due in early 2008. Hopefully, we’ll get a preview of the instruction set and the initial offerings at the Alliance Partner Conference coming up in December.
