MICROSOCKETS.COM: Embedding the Network

We received word that the long awaited Professional version of HI-TECH C for the PIC 10/12/16 has been delayed.  The new release date is scheduled for Jan/Feb of 2008, which gives another solid month after the holidays for HI-TECH to wrangle the remaining bugs.

Here’s the announcement from HI-TECH:

“As is the case from time to time, we experience some extraordinary product development challenges. The release phase for HI-TECH C PRO for the PIC10/12/16 MCU Family (PICC PRO) has been no exception. As a result of these challenges the Beta Testing period of the HI-TECH C PRO for the PIC10/12/16 MCU Family has been extended; with the final release scheduled for the end of January/ early February 2008.

“We realize this delay may not fit with your timelines. Please be assured that if there is any way we can get the product to you earlier, we will.”

For those who are not familiar, the Pro version of the popular HI-TECH C Pro compiler adds Omniscient Code Generation™ which provides aggressive cross-module optimizations that can produce significant code size and performance improvements.

 The beta program has been extended and you can still sign up on the HI-TECH site at this link.

On November 8, 2007, Renesas provided an update on the progress of its new 16/32-bit CISC architecture. The new family finally has a name- RX Family – where RX implies ”Renesas eXtreme.”

The new CPU is the long-term replacement or migration path for the collection of products created by the merging of Mitsubishi and Hitachi product portfolios.  The RX replaces the H8S, M16C, M32C, R32C and H8SX with a unified, high-performance processor architecture.

• 200 MHz operating frequency
• 1.25 MIPS/MHz performance
• 30% reduction in code size compared to previous CISC architectures
• Low power consumption – 0.03mA/MHz

The boosts in operating frequency and instruction efficiency promise a 12.5 times increase in performance over existing Renesas CISC controllers.

Much of the presentation is a rehash of the May 2007 announcement with some clarifications and specifics that reflect the progress of development.   Here are some key differences from previous announcements.

• Silicon availability in Q2 CY2009 – moved up from Q3 CY2009
• 1/3 power consumption measured mA/MHz – down from 1/2 versus M16 and H8
• Processing performance at 1.25 MIPS/MHz up from 1.0 MIPS/MHz

Other than the name, which is better suited for an energy drink or deodorant, there is a lot to like hidden in the details of the presentation.

• 32-bit multiplier, divider and MAC (32 x 32 + 80 bits)
• Variable length instructions optimized for common operations
• 16 32-bit registers to support compiler optimization
• Selectable big-endian (H8S) and little-endian (M16C) data access
• C-friendly addressing modes for improved pointer manipulations
• C-level compatibility with previous devices and common peripherals
• On-chip single-precision FPU that utilizes the general register set

Processor specifications are due in early 2008.  Hopefully, we’ll get a preview of the instruction set and the initial offerings at the Alliance Partner Conference coming up in December.

MICROCHIP pulled the trigger on their new PIC32 family of microcontrollers today.  As we suspected, they have teamed up with MIPS to provide a single-chip 32-bit microcontroller platform aimed squarely at the ARM empire.

MICROCHIP gets an established and respected core and MIPS gets tied to an established set of peripherals, integrated toolchain, distribution network, field support team and a growing set of design partners (including Microsockets!). 

Official Particulars of the PIC32MX:

• 72MHz MIPS32 M4K core with MAC 
• 64 or 100 pin TQFP
• PIC32MX300F032H: 64-pin, 32K Flash,  8K RAM, $2.95 QTY10K
• PIC32MX360512L: 100-pin, 512K Flash, 32K RAM, $5.30 QTY10K
• Volume production Q2 2008
• C32 Compiler available now
• Explorer16 compatibility
• ICD2, RealICE, MPLAB support now

Initial Peripherals:

• 10-bit ADC, 16 channels
• 5 Timers with capture and compare
• 2 UARTS, 2 SPI, 2 I2C
• POR, BOR, LVD

Initial code examples include TCP/IP with HTTP, FTP, SMTP for the SPI-based Microchip ENC28J60 10Mbps MAC/PHY running on the Explorer 16. In addition to a $25 PIC32 PIM for the Explorer 16, a PIC32 Starter Kit is available for under $50.

Overall it’s a pretty exciting announcement that 10 years ago would have sounded totally ludicrous.  Now if I can just get MPLAB to connect to my SGI Indy.

We’ve heard promises of big news coming from Microchip in November with confirmation of impending announcements from company field reps.  Unfortunately, what exactly is coming down the pipeline is a big mystery and we are left to pure speculation.

MASTERS 2007 was surprisingly quiet with a keynote speech from Steve Sanghi devoid of new product information.  FAEs and sales reps have been tight-lipped but enthusiastic about the impending announcement.

So we are left with big expectations for filling the holes in Microchip offerings.

The Obvious Choice – PIC32

The cost differential between 8-bit and 32-bit single chip microcontrollers is rapidly evaporating.  Low cost single chip microcontrollers such as the ARM Cortex parts are creeping down to very competitive levels.  New embedded applications are increasingly requiring USB, onboard Ethernet, wireless and LCD features.  While current Microchip offerings support these features, they need a solution that supports the connectivity features and the embedded application on a single chip.

The Q2 2008 conference call featured the direct question regarding when will there be a 32-bit offering and received a well orchestrated non-response from the management team.

Filling in the Gaps – Microchip C8

Microchip has long focused on development tool shipments to predict future market growth and product adoption.  Fewer and fewer developers are opting to kick out assembly code no matter the size of the processor.  When CCS is the best selling C compiler for your chip, its time to look at taking control of the user experience.

Maybe it’s just wishful thinking, but a low-cost C compiler that is designed to plug into MPLAB is just what the doctor ordered to fight off Atmel’s juiced-up 8051 variants, Freescale’s Black Widow HC908s and TI’s onslaught of MSP430s.

Not Likely – MICROMIPS

With MIPS entering the 32-bit MCU market, who is going to adopt their IP?  Other than Freescale, which seems to collect 32-bit architectures like they stick to their shoes, who is going to bring MIPS to the masses? As in the 8-bit market, everybody wants to be Microchip,  in the 32-bit market everybody wants to be ARM.  While they would make strange bedfellows, Microchip can deliver the customers if MIPS can deliver the cores.

Again, not likely.  Not Microchip’s style.  Not the kind of partner MIPS is looking for.  But, with long-term double-digit annual growth projected for 32-bit MCUs and ARM sitting comfortably atop the design IP market, strange things are bound to happen.

What have you heard?

Let us know what you’ve heard or what you think is coming.  And let’s hope that it is something big.

Renesas recently announced its first annual Alliance Partner Conference, scheduled for December 4-5, 2007 in Durham North Carolina.  The invitation only conference is intended to build ties between Renesas and its Alliance Partners. 

Given that Research Triangle Park is the headquarters for Renesas software tool development in the United States, we can expect a strong turnout from Renesas software and application engineers.  The initial conference outline is heavy on HEW – the integrated Renesas development toolchain.  Hopefully we will receive some clarity on the future of the Renesas silicon offerings and the new CISC architecture promised for 2008.

 More information is forthcoming, but be sure to look for MICROSOCKETS at the conference.  Also, do yourself a favor and make time for a dinner at The Capital City Chop House.

Cleveland is a late addition to the MSP430 Advanced Technology Seminar schedule.   TI promises the latest information on new releases and in-depth  discussions on low-power applications straight from the experts.

If you are new to the 430 series, its claim to fame is its ultra-low-power 16-bit architecture supporting cost-sensitive, battery operated applications.  MSP430s feature a mixed-signal design and a high performance 16-bit RISC CPU.  The architecture is designed to minimize power use through a variety of lower power modes (LPM0-LPM4), shorter transition times between modes and faster execution program code. The faster the chip starts up and executes the application the more time it can spend sleeping and saving precious power.

This event focuses on the MSP430F2xx series of devices.

Additional information and a registration links are available here.  Look for Microsockets at the Cleveland event on November 29.

Welcome to the Microsockets blog. A blinking LED would be more appropriate but we’ll have to settle for a tribute to the K&R C classic.

Look for posts on the following topics in the coming months on the blog:

• Information on upcoming Microsockets product releases
• Support for existing Microsockets products
• Informal discussion about embedded systems and related technologies
• Introductions to Microsockets partners and customers
• Announcements of local and national industry events

Drop us a line if there is something you’d like us to cover.